OOPSLA '04

Program
Technical Program
  Invited Speakers
  Technical Papers
  Onward!
  Panels
  Practitioner Reports
  Tutorials
Workshops
DesignFest
Educators' Symposium
Demonstrations
Posters
Doctoral Symposium
Exhibits
Student Research Comp.
FlashBoF
 
Turing Lecture
 
Social Events
 
Week at a Glance
 
Final Program (1.5M .pdf)

Find in Program
 

Page
Printer-friendly

Basket
view, help

"3rd International Workshop on Language Runtimes: "Impact of Next Generation Processor Architectures On Virtual Machine Technologies""
Object-Oriented Programming, Systems, Languages and Applications
Home    Program    Housing & Transportation    Registration    Submissions    Wiki    Maps
 
  > Workshops

 : Thursday

3rd International Workshop on Language Runtimes: "Impact of Next Generation Processor Architectures On Virtual Machine Technologies"

Meeting Room 14
Thursday, 8:30, full day
 


 
7·8·9·10·11·12·13·14·15·16·17·18·19·20·21

Yahya Mirza, Aurora Borealis Software LLC
Aart Bik, Intel Corporation
George Bosworth, Microsoft Corporation
Tarek El-Ghazawi, George Washington University
Mootaz Elnozahy, IBM Austin Research Labs
Alexander Garthwaite, Sun Microsystems Laboratories
Vinod Grover, Microsoft Corporation
Richard Lethin, Reservoir Labs, Inc
Timothy Mattson, Intel Corporation
Mark Mendell, IBM Canada

http://www.aurorasoft.net/workshops/lar04/lar04home.htm

Next generation applications in both the scientific and entertainment arenas are starting to converge in their requirements for extensive data-level parallelism. Furthermore, parallel processing technology is becoming pervasive throughout all computing systems. For example, Sony, Toshiba and IBM are developing the CELL processor architecture to serve as the core processor technology for a range of devices from PDAs and game consoles to Supercomputers.

Although there is a great opportunity for performance by leveraging grids consisting of these architectures, we must also consider the difficulty and cost of programming these systems. Unfortunately, the execution models of today's virtual machines are geared primarily towards basic scalar processors. As the characteristics of these architectures (e.g., system on chip, multi-processor cores, simultaneous multi-threading, polymorphic architectures, vector units, stream processing, DSP coprocessors, etc.) are better understood, it will be necessary to minimize the mismatch of our virtual machine execution models with these new processor architectures.